Extremely small nonvolatile memory cells are required for a very large scale integration density in multimedia applications. The further development of semiconductor technology is making possible increasingly larger storage capacities, which will very soon open up the gigabit range. However, while the minimum feature size determined by the lithography continues to decrease, other parameters, such as, e.g., the thickness of the tunnel oxide, can no longer be scaled correspondingly. The decrease in the channel length, which accompanies the structural miniaturization in the case of planar transistors, requires an increase in the channel doping in order to avoid the occurrence of a voltage breakdown—referred to as punch-through—between source and drain. This leads to an increase in the threshold voltage, which is usually compensated for by reducing the thickness of the gate oxide.
However, planar SONOS memory cells (see Boaz Eitan U.S. Pat. No. 5,768,192, U.S. Pat. No. 6,011,725 and WIPO Patent Publication 99/60631) that are programmable by means of channel hot electrons and erasable by hot holes require a control dielectric having a thickness equivalent to a gate oxide. This thickness cannot be reduced arbitrarily, however, without the number of executable programming cycles (“endurance” of the memory cell) decreasing in an unacceptable manner. Therefore, a sufficiently large channel length is necessary in order that the dopant concentration in the channel does not have to be chosen to be excessively high, because otherwise the threshold voltage rises too much.
The publication by J. Tanaka et al.: “A Sub-0.1-μm Grooved Gate MOSFET with High Immunity to Short-Channel Effects” in IEDM 93, pp. 537–540 (1993) describes a transistor on a p+-type substrate, in which the gate electrode is arranged in a trench between the n+-type source region and the n+-type drain region and a curved channel region is thus formed in the substrate.
The publication by K. Nakagawa et al.: “A Flash EEPROM Cell with Self-Aligned Trench Transistor & Isolation Structure” in 2000 IEEE Symposium on VLSI Technology digest of Technical Papers describes a transistor as memory cell with a floating gate electrode which is arranged between the n+-type source region and the n+-type drain region in a manner such that it reaches right into a p-type well of the substrate. A dielectric layer made of an oxide-nitride-oxide layer sequence is situated between the floating gate electrode and the control gate electrode.